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Bit-Serial Architecture Optimizations: Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit?Serial Fully Pipelined Architecture: 9783639328172: Computer Science Books @ Amazon.com
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PDF) 1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro | Subramanian S Iyer - Academia.edu
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A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
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An FPGA-based processing pipeline for high-definition stereo video | EURASIP Journal on Image and Video Processing | Full Text
